The present invention relates to magnetic memory devices and is applicable to magnetic memory devices capable of storing data by giant magneto-resistive effect or tunneling magneto-resistive effect.
Studies have been conducted on nonvolatile magnetic storage semiconductor devices (MRAM: Magnetic Random Access Memory) utilizing the tunneling magneto-resistive (TMR: Tunneling Magneto-Resistive) effect by ferromagnetic tunnel junction. An example of prior literature on the TMR element is Patent Document 1. In this specification, the term of TMR element is used as a concept including MTJ (Magnetic Tunnel Junction) element.
The TMR element disclosed in Patent Document 1 has a three layered laminated structure of fixed layer/insulating layer/free layer. In the magnetic memory device disclosed in Patent Document 1, a current is passed through a selection bit line (selection BL) and a selection digit line (selection DL). Thus a combined magnetic field is produced at the intersection between the selection BL and the selection DL and the orientation of magnetization of the free layer composing a TMR element can be changed (writing of data). By passing a current through a TMR element and detecting the resistance value thereof, reading of data is executed. The resistance value of the TMR element varies depending on whether the orientation of magnetization in the fixed layer and that in the free layer are identical or opposite.
In the MRAM according to Patent Document 1, the write characteristic is improved by specifying the shape of the TMR element. The shape of this TMR element is asymmetric in the direction of an axis on which magnetization is easy and symmetric with respect to an axis perpendicular to the axis on which magnetization is easy. (Hereafter, the shape of the TMR element is simply referred to as asymmetric shape.)
The above MRAM is comprised of an element selection transistor and a TMR element having the above asymmetric shape. In the above MRAM, the TMR element is arranged between a bit line (BL) extended in a first direction and a digit line (DL) intersecting the BL as viewed on a plane. The TMR element is formed over a strap wiring (also referred to as local strap (LS)). In addition, the above MRAM includes a top via (TV) for coupling a TMR element and BL and a local via (LV) for coupling LS and either electrode area of an element selection transistor. These vias are required to read data. The other electrode area of the element selection transistor has a source line (SL) coupled thereto. The gate electrode of the element selection transistor becomes a word line (WL). The SL and the WL are also required to read data.
The other prior literature related to the MRAM includes Patent Document 2. Patent Document 2 proposes a cell structure comprised of one element selection transistor and four TMR elements.
[Patent Document 1]    Japanese Unexamined Patent Publication No. 2004-296858
[Patent Document 2]    Japanese Unexamined Patent Publication No. 2006-294179